LatticeMico DMA Controller      

Version

Description

3.3

Added software support for LatticeMico8.

3.2 (8.1 SP1)

The data busses on the three WISHBONE interfaces can be configured to be 8 or 32 bits. Support added for handling WISHBONE RTY (retry) for burst transfers. Support added for handling WISHBONE ERR (error). Register map updated to support 8-bit and 32-bit WISHBONE data bus.

3.1 (8.0)

DMA Engine upgraded to comply with Rule 3.100 of Wishbone Specifications, which deal with byte alignment for transfers that are less than the width of Wishbone data bus.

3.0 (7.0 SP2)

Because the read and write channel worked in parallel, the write channel started writing data to the slave as soon as the FIFO is not empty.

Increased burst size to support bigger bursts from a current value of 4 and 8 to 16 and 32, respectively. DMA now supports four burst sizes: 4, 8, 16, and 32. The Burst Size field of the control register was increased to 2 bits.

A glitch was removed on the S_ACK_O signal.

1.0

Initial release.

Parameter

Description

Instance Name

Specifies the name of the DMA controller instance. Alphanumeric values and underscores are supported. The default is dma.

Base Address

Specifies the base address for accessing the internal registers. The minimum boundary alignment is 0X80. Supported values are 0X80000000 to 0XFFFFFFFF. The default is 0X80000000.

FIFO Implementation

Determines whether the FIFO is implemented as an EBR or a LUT. The default is EBR.

Retry Timeout

Specifies the number of WISHBONE clock cycles that the DMA controller must wait after the source or destination asserts the WISHBONE RTY before retrying the same WISHBONE cycle.  Supported values are 1 to 255. The default is 16.

WISHBONE Configuration

Control Port Data Bus Width

Configures the control port's WISHBONE data bus to be 8 or 32 bits wide.

Read/Write Port Data Bus Width

Configures the read and write WISHBONE master port data buses to be 8 or 32 bits wide.